An off-chip pad driver is primarily used to provide data at the output pad that transmits data to a receiver contained in another chip which may be located at quite a distance. The receiver is triggered by this data, hence, it may be required that it receives a good signal in terms of amplitude, frequency and noise level at its input. To transmit data at high-speed, it may be essential to maintain a noise immunity level in conjunction with the rise and fall slew rates of the driver being appreciably high. In some cases, the driver may be used in different environment where the capacitive load, driven by the pad driver, varies to a large extent.
FIG. 1 shows the prior art pad driver circuit. EN is the tri-state signal connected to one of the inputs of NAND gate 4 while the other input of the gate 4 is a data signal (DATA). The EN signal is also connected to the input of the inverter 2, the output of which is connected to the input of NOR gate 6. The DATA signal acts as second input of the NOR gate 6. The core provides both the signals. The pull-up section of the driver contains P-channel transistors 14 and 16 whereas the pull-down section of the driver contains N-channel devices 18 and 20. Transistors 16 and 18 are provided for specific purposes like providing process compensation etc.
A high logic level at the EN signal enables the driver and passes the data. When the data switches from a low logic level to a high logic level, the pull-up transistors switch at a slower rate than the pull-down transistors. The pad achieves the high logic level. When the data switches from a high level to a low level, the pull-down transistors transit at a slower rate than the pull-up transistors, thereby making the pad achieve the low logic level. This mechanism helps to remove the crowbar current though the driver.
The performance of the driver may be very good for a given load, but its use may be limited to a particular application. Also if the driver is made small considering minimum load conditions, it may become useless for high load applications at the given speed, whereas if it is made larger to provide higher drive, the noise level at lower load environments is high thus degrading driver performance.
Another prior art circuit is presented in U.S. Pat. No. 6,597,199 with the title “Method and circuit for logic output buffer” as shown in FIG. 2. It provides the benefit of faster switching, low switching noise and improved switching time, but it does not depict dynamic control on the voltage slew rate control with respect to capacitance variation at the pad. Further details can be referred to from the patent.
Yet another prior art circuit is presented in FIG. 3 of U.S. Pat. No. 6,583,644 titled “Output buffer for reducing slew rate variation”. It uses a slew rate compensator for minimizing slew rate variation caused by the change in the load capacitance at the pad terminal. It compensates for the slew rate through coupling of the pad voltage with the driving stage. However the circuit has following disadvantages.
Reduced slew rate variation is achieved though capacitive coupling of the complementary signal ultimately slowing the signal at the pad. Therefore, the size of the driver and the pre-driver circuit increases for a given drive. It also increases the power dissipation of the circuit.
For high-speed design, when signal switching is fast, capacitive coupling may not be effective. The circuit, therefore, does not take care of the capacitance variation at the pad.